1. Field of Invention
This invention relates to MRAM magnetic random access memories in general and is particularly applicable to a device for setting up a write current on at least one write conducting line in an MRAM type integrated circuit memory.
2. Discussion of Related Art
Magnetic random access memories (MRAM) are non-volatile type memories. Typically, a magnetic random access memory device comprises a matrix of memory cells arranged in rows and in columns, through which metallic tracks are routed. The metallic tracks extending along memory cell rows are called word lines and the metallic tracks extending along memory cell columns are called bit lines. Each memory cell thus located at the intersection of a word line and a bit line stores an information element in the form of a magnetization orientation.
Each memory cell is composed of two magnetic layers separated by a dielectric layer. Each magnetic layer has its own magnetization orientation. The magnetization orientation of one of the layers, called the free layer, can be modified, while the magnetization orientation of the other layer, called the fixed layer, is fixed in a particular orientation. The magnetization orientations of the two layers can be one of two situations: they are either parallel, in other words aligned along the same direction, or anti-parallel, in other words are aligned in opposite directions. These two orientations, parallel and anti-parallel, represent the logical values “1” and “0” respectively. As a variant, the parallel state may be interpreted as a logical “0” and the anti-parallel state may be interpreted as a logical “1”.
Starting from this point, writing for such a memory cell consists of setting the magnetization orientation in the free layer as a function of the required logical state, either in a parallel state or in an anti-parallel state, with respect to the magnetization orientation of the fixed layer.
Typically, external magnetic fields are applied onto a selected cell to trigger the magnetization orientation in the free layer of this cell from one state to another. To achieve this, a write current is applied on the word line and on the bit line respectively intersecting at the location of the selected memory cell. The write currents are thus applied on the selected word line and bit line, creating magnetic fields which may combine at the intersection of the word line and the bit line to switch the magnetization orientation of the free layer of the selected memory cell from the parallel state to the anti-parallel state or vice versa, as a function of the data to be written in the cell.
High magnetic fields are necessary to change the state of a memory cell selected in write from one state to another, which requires that sufficiently high write currents of the order of ten milliamperes are circulated on the metallic tracks making up the word lines and bit lines at the intersection of which the memory cell selected in write is located. Consequently, it is necessary to be able to control the value of the intensity of the write current circulating on the metallic tracks with high precision, and also the rate at which rising and falling fronts of the write current intensity are set up.
Some constraints must be considered during the phases of setting up and stopping the current pulse necessary to change the magnetization of an MRAM memory cell for programming the cell. Thus, if the gradient of the current pulse is too high during the setting up phase, in other words if the current level necessary to program a cell is set up too suddenly, oscillation phenomena may occur consequently inducing a high instability in the magnetization orientation of the memory cell selected in write. Therefore the rate at which the write current is set up has to be relatively low to avoid this problem. However, the duration of the write cycle will be longer if the current set up speed is lower. As a result, a compromise has to be found in the gradient of the write current pulse, so as to avoid oscillation phenomena while not penalizing the duration of the write cycle, which is an important parameter for memories in general.
U.S. Pat. No. 6,657,889 in the name of the Motorola Company describes an MRAM type memory device in which the write circuitry is based on a sequence of several current mirror stages and which includes means of checking the write current set up gradient. FIG. 1 in the present application illustrates part of the write circuitry of the MRAM memory device according to U.S. Pat. No. 6,657,889, in a simplified manner.
A matrix of MRAM type memory cells is shown by the box reference 100 shown in dashed lines in FIG. 1. The matrix 100 includes a plurality of write bit lines and a plurality of write word lines, typically 128 or 256 lines, at the intersection of which memory cells are located, not shown in the Figure. Only two write word lines, WL0 and WL1, are shown in order to simplify the explanation. The associated write circuitry that will be described below is obviously located in a similar way on the bit lines of the memory cells matrix.
A power supply Vdd is connected to one end of each of the word lines WL0 and WLl. The other end of each of the write lines WLO and WL1 is connected to the drain of an NMOS transistor 102 and 104 respectively, dedicated to addressing of memory cells of the matrix. The transistor grid 102 is connected to a control signal Rdec0 output by an address decoder and its source is connected to a current mirror 110 through a conductor 106. The transistor grid 104 is connected to a control signal Rdecl output by the address decoder and its source is connected to the current mirror 110 through the conductor 106. NMOS transistors 112, 114, 116 and 118 form the current mirror 110, which is provided with a reference current Iref having a value of several milliamperes. The branch composed of the transistors 116 and 118 of the current mirror stage 110 is made conducting during a write cycle when a synchronization signal Xpulse is activated on the grid of the transistor 118. The transistor 116 thus provides analog control of the current output by the current mirror 110, while the transistor 118 manages the duration of the write current pulse. Thus, when the write cycle relates to a memory cell in word line WL1, the transistor 104 is made conducting by activating the control signal Rdec1 and the copy current Iref is set up on word line WL1 once the Xpulse signal is activated. The pulse gradient of the write current is controlled by transistor junction capacitors precharged to a determined potential. An equivalent method is used for the bit line corresponding to the addressed cell.
The architecture proposed by U.S. Pat. No. 6,657,889 provides relatively good precision of the write current obtained by copy in the current mirror, however with a constraint to achieve this result. The transistor 116 must thus necessarily operate in the saturated zone. In this operating mode, the saturation current of a transistor is slightly dependent on the voltage on its drain. For operation of transistors in the saturated zone, the condition to be respected is that Vds≧Vgs−Vt (1), where Vds is the drain-source voltage of the transistor, Vgs is the grid-source voltage and Vt is the threshold voltage of the transistor.
The conducting tracks making up the word lines are inherently resistive. The fact of circulating a high current of the order of about ten milliamperes in word line WL1 will therefore inevitably cause a drop in the potential Vb at the end of the word line (by application of Ohm's law) and consequently a voltage drop at the drain of the MOS transistor 104, and transistor 116 of the current mirror. Therefore, the drain-source voltage of the transistors will drop, which could result in the transistors operating in their linear zone. In this case, it is no longer possible to guarantee that the current is copied with good precision at the word line WL1.
To maintain operation under saturation conditions despite the potential drop at the end of line WL1, U.S. Pat. No. 6.657,889, specifies that MOS transistors operating with a low grid-source voltage Vgs should be used, such that condition (1) is respected over the widest possible operating range. A MOS transistor that operates with a low grid-source voltage and that is nevertheless designed to carry a high current, must be large in size, typically on the order of 1 mm wide. Thus, the precision of the current copy which in this solution according to prior art is directly related to a saturated mode operating condition of the transistors, is obtained at the detriment of the size of the transistors forming the current mirror, which can reduce the memory integration density.
However, if the potential drop at the end of the line is such that Vb<1 V, it becomes very difficult to keep transistors operating under saturated conditions when current is passing, even if they are large. Therefore a high end of line voltage has to be maintained, at least Vb>1 V, to be able to hope that the assembly can be operated with the required precision.